AutoC Empowers ST SR6P3ECR52 MCAL Configuration (Part 1): Pain Points, Knowledge Base Setup, and Hands-on Clock/Pin/DIO Configuration

①The chip RM manual has thousands of pages, and manual calculations such as frequency division, channel, and DMA mapping parameters are extremely error-prone;

②Multi-module linkage configuration easily misses bidirectional related items;

③When troubleshooting problems, you need to rely on tools such as Git to compare differences one by one. There are too many files involved, making it difficult to roll back, and the debugging efficiency is extremely low.

1. Full-link traceability inquiry

Any clock, channel, and DMA parameters can be dialogued to inquire about the derivation logic. AI outputs manual tables, EB plug-in formulas, verification steps, etc. Engineers can check the manual for a second time to synchronize standardized configuration ideas.

2. Independent change rollback system

There is no need to rely on Git. Each round of configuration generates a complete change list, clearly displaying the parameters "original value → new value"; it supports global one-click rollback and individual parameter undoing, and local debugging does not require repeated generation of the entire set of configurations.

1. Knowledge base import operation logic

AutoC supports splitting the complete chip RM manual into independent PDF documents according to functional chapters such as clock, PORT, DMA, communication peripherals, etc., and importing them into the knowledge base in batches. All AI generation parameters, hardware constraints, and timing rules strictly follow the original logic of the import manual, which can effectively eliminate the need to break away from the hardware and generate configurations out of thin air that appear to be compliant but are actually inoperable.

AutoC knowledge base document management interface

2. Engineering docking method

Directly load the existing EB Tresos project, interactively issue configuration requirements through natural language dialogue, AI reads the project plug-in Schema, enumeration parameters, and hardware constraint formulas in real time, and simultaneously combines the knowledge base chip manual with double verification to output the configuration plan.

1. Pitfalls in initial configuration: vague requirement description triggers scaling

Hardware 20MHz external crystal oscillator, target PLL0:PHI/PHI_JM=400MHz. For the first time, only the crystal oscillator frequency is informed. The AI scales proportionally according to the 40MHz example in the manual, and the output is only 200MHz.

Figure 1: Initial clock generation results

Figure 2: AI scaling logic description

2. Accurate correction: After clarifying the requirements, a compliant clock tree is generated

Supplementary constraints: the crystal oscillator is changed to 20MHz, the PLL target remains at 400MHz, the AI redistributes the frequency division/multiplication coefficient, and the VCO reaches 800MHz; the peripheral clock follows the rules and tries to reach the full frequency within the hardware allowable range. If it cannot be divided evenly by 10MHz, it will be rounded down, and finally the EB check zero error will be reported.

Figure 3: Corrected complete PLL & peripheral clock configuration

3. Clock traceability query and review

If you have questions about the clock distribution logic, you can directly ask AI and the tool will output the four-layer verification basis step by step:

①Read all legal clock enumeration candidates of the MCU module;

② Retrieve the chip manual clock tree table and lock the exclusive clock branch of each peripheral;

③Verify the actual output frequency so that it does not exceed the maximum hardware limit;

④ Engineers can review the manual one by one through the AI path to fully grasp the clock tree design logic.

4. Practical expansion of ideas

During project development, most scenarios only require minor fine-tuning based on the original chip reference clock. The chip clock manual knowledge base can be imported in advance, and the existing clock reference and hardware frequency boundary values of the project can be read through dialogue commands. Peripheral fine-tuning commands can be issued on demand to quickly iterate the clock solution.

After importing the HSI hardware table, the system calculates PortPinPcr according to the functional grouping requirements and based on the ST P3E hardware formula; this process will automatically correct pin naming and hardware mode conflicts (such as PB11 FCCU mode adaptation), and list conflicting items for manual confirmation.

Figure 4: Port pin configuration details

Figure 5: EB Project Port Grouping Interface

Figure 6: Partial pin Port detailed configuration table

1. Automatic mapping calculation logic

After the GPIO configuration of the PORT module is completed, a single instruction can generate DIO configurations in batches and automatically allocate 84 GPIO channels to 14 independent DioPort ports.

Engineers can query the ID conversion source through dialogue, use AI to call the original Schema of the DIO plug-in to display the calculation formula, and clearly explain the corresponding relationship between the PCR index and the port and channel, eliminating configuration doubts.

Figure 7: Dio port channel mapping summary table

2. Optimization of custom port naming

Optimized readability: The command renames DioPort_0 to DioPort_A with one click. The channel name simultaneously uses the PORT pin identification, and no errors are reported during the entire verification process.

Figure 8: Dio port renaming comparison table

Figure 9: EB Engineering Dio port group directory

Zhongke Yichuang (Guangzhou) Technology Co., Ltd. was incubated and established by the Greater Bay Area Integrated Circuit Research Institute. It is a key investment incubation project of the Chinese Academy of Sciences and has received key support from the Guangdong Provincial and Municipal Governments. The company has won many honors such as National High-tech Enterprise, Guangdong Province Specialized and New Enterprise, and Guangdong Province Top 100 Hard Technology Enterprises.

Currently, Zhongke Yichuang has its Guangzhou headquarters, Wuxi manufacturing base, Shanghai branch and Wuhan delivery center. The company focuses on the development of power bricks, motor controllers and domain controllers in the field of new energy vehicles. It not only obtained the first ASIL-D SiC motor controller product certification in China, but also passed many authoritative vehicle-level qualification certifications such as IATF16949, ASPICE L2, ISO9001, etc., showing strong system strength. In addition, the company has a complete set of capabilities in software, hardware, structure, testing, production and manufacturing, and has been recognized and praised by many OEMs.